Today's very high capacity and high performance storage systems can include hundreds of terabytes of storage. It is preferable for performance reasons to include cache memory systems within such storage systems in order to increase data transfer rates between the storage system and the host systems that access the storage system. Because the capacity of the storage system is so large, very large cache memory systems are preferably provided to maximize performance. However, providing a high bandwidth, scalable memory system containing thousands of individual memory devices presents a design challenge. The thousands of memory devices present very wide bus widths to which controllers must interface. Furthermore, the memory devices are so many that the boards on which they reside are large and physically distant from each other, which presents signal integrity issues at high speeds. It would be desirable to provide a high bandwidth, scalable memory system in which pin count and signal integrity issues are efficiently dealt with.